Area-Delay Efficient Hybrid Ling–Kogge–Stone Adder for High-Speed Processing

Abstract

The adder is a crucial component of the Arithmetic Logic Unit (ALU) in contemporary high-performance VLSI computers. and frequently sets a processor\'s maximum clock frequency. This project demonstrates the creation and implementation of a 32-bit Hybrid Ling–Kogge–Stone (LKS) adder that combines the high-speed parallel prefix structure of the Kogge–Stone adder with the lower logic cost of Ling\'s carry formulation. Performance is negatively impacted by increasing fan-in and logic depth in the first carry-propagate stage of conventional Kogge-Stone adders. The suggested architecture effectively removes one logic step from the critical route and streamlines carry generation by utilizing Ling\'s transformation. Verilog HDL is used to model the Hybrid LKS adder, and the Xilinx Vivado Design Suite is used to synthesis it. Improved signal integrity and high-speed operation are ensured by using a five-level parallel prefix tree to achieve an delay while retaining a maximum fan-out of two at each node. Compared to traditional RippleCarry and ordinary Carry LookAhead adders, post-synthesis results show a notable decrease in Total Combinational Path Delay (TCPD). Additionally, a thorough examination of Area, Power, and Delay (PPA) validates the effectiveness of the suggested design. The Hybrid LKS adder is ideal for high-performance RISC-V execution units and cryptographic accelerator applications because of its exceptional speed performance and scalable architecture.

Introduction

This paper focuses on the design and optimization of Approximate Parallel Prefix Adders (PPAs) for VLSI systems, where high speed, low power consumption, and reduced hardware area are critical. PPAs such as Kogge-Stone (KS) and Ladner-Fischer (LF) are widely used in processors and digital signal processing systems because they perform fast binary addition. Approximate adders are preferred in applications where a small error is acceptable, as they can achieve lower delay, power consumption, and area compared to exact adders.

Background and Motivation

Traditional PPAs aim to minimize delay, area, and error rates. Approximate Computing (AxC) introduces controlled inaccuracies to improve system efficiency, making it suitable for applications like image processing where perfect precision is not always necessary. This approach helps reduce circuit complexity, hardware area, and energy consumption.

Existing Parallel Prefix Adders

• Kogge-Stone Adder (KSA):
  • A high-speed carry look-ahead adder developed in 1973.
  • Generates carry signals efficiently with low latency.
  • Commonly used in 32-bit and 64-bit high-performance systems.
• Ladner-Fischer Adder (LFA):
  • Uses a tree-based carry generation structure.
  • Optimizes area by reducing the number of logic cells.
  • Suitable for approximate designs where minor inaccuracies are acceptable.

Proposed Approximate Kogge-Stone PPA

The proposed 32-bit Approximate Kogge-Stone PPA is divided into:

1. 8-bit approximate section (LSB bits 0–7):
   • Uses logical OR operations for faster computation.
   • Produces approximate sums and carry output.
2. 24-bit exact Kogge-Stone section (bits 8–31):
   • Uses the carry from the approximate section.
   • Produces accurate higher-order sum bits.

This hybrid structure reduces delay while maintaining acceptable accuracy.

Proposed Hybrid PPA1

The proposed Hybrid PPA1 combines:

• An 8-bit approximate adder (bits 0–7)
• A 12-bit exact Kogge-Stone adder (bits 8–19)
• A 12-bit exact Ladner-Fischer adder (bits 20–31)

This architecture balances speed, area efficiency, and accuracy by using approximate computation only in lower-significance bits.

Simulation Results

Simulation comparisons were performed between:

• Exact Kogge-Stone Adder
• Existing Approximate Kogge-Stone (AxKS)
• Proposed Approximate Kogge-Stone (AxKS)

Key findings:

• The proposed AxKS adder achieved slightly lower error rates than the existing AxKS design.
• It reduced delay and hardware resource usage while maintaining high performance.
• For a 32-bit design:
  • Exact KS Delay: 17.460 ns
  • Existing AxKS Delay: 7.086 ns
  • Proposed AxKS Delay: 7.084 ns

Performance Analysis

Among the proposed 32-bit approximate PPAs:

The Proposed Approximate Kogge-Stone PPA (AxKS) achieved the lowest delay (6.975 ns), making it the fastest design among the evaluated architectures.

Conclusion

This work has looked at, simulated, and assessed several approximation adders. The results of the experiment were subsequently put into practice. In order to achieve high PSNR values and reduced area and delay, new parallel prefix adders were developed and installed for this project. This addition method is very quick and produces better results when applied to huge numbers in a much shorter amount of time. The suggested Ax parallel Prefix adders show promise for use in image processing, ALU units, and digital signal processing. Applications for picture contrast and enhancement are used in this study.

References

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Copyright

Copyright © 2026 AP Harini Sree, D.Srinivasulu Reddy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.