CMOS Logic Design Using Neural Networks

Abstract

This paper presents the design of digital logic functions using analog neural network principles. The logic gates are implemented as a single-layer perceptron neuron: MOS transistors fed by inputs with widths proportional to synaptic weights add up drain currents at a shared node via Kirchoff’s current law, MOS transistors biased by a reference voltage to provide the threshold offset, and a cascaded CMOS inverter pair to perform a step activation function. This neuromorphic approach is demonstrated by designing a NOT gate, a NAND gate and an 1-bit full adder. The full adder resolves the non-linearly separable XOR problem by cascading two neurons; a majority-gate Carry output neuron followed by a Sum output neuron that uses the Carry as a double weighted inhibitory input. TSMC 180nm CMOS process is used for the implementation. Electric VLSI tools are used for making transistor schematics and layout. Simulations are carried out using LTspice. The 23 transistor neural network full adder achieved propagation delays less than 0.5ns and 0.27ns for the sum and carry outputs respectively, with an average power of 1.3mW. For comparison purposes, a fully complementary CMOS full adder using 36 transistors was also designed.

Introduction

This paper explores the use of Artificial Neural Networks (ANNs) in the design and implementation of digital logic circuits, specifically NOT and NAND gates, and a full adder. Inspired by the biological structure of the human brain, ANNs consist of interconnected artificial neurons that process information in parallel, enabling faster and more efficient computation. Due to these advantages, neural networks have found applications in areas such as pattern recognition, speech processing, image processing, and earthquake prediction.

A neural network is composed of an input layer, one or more hidden layers, and an output layer. Each artificial neuron contains inputs, weights, a bias, and an activation function. The simplest type of artificial neuron is the perceptron, whose output is determined by the weighted sum of its inputs and bias, followed by a step activation function that produces binary outputs (0 or 1).

The paper demonstrates how logic gates can be modeled as perceptrons by selecting appropriate weights and bias values. For the NOT gate, a single input perceptron with a weight of –1 and a bias of 0.5 correctly produces the inverse of the input. When the input is 0, the output is 1, and when the input is 1, the output is 0. The authors note that several combinations of weights and biases can achieve the same logical function.

Similarly, a 2-input NAND gate is implemented using a perceptron with weights –1 for each input and a bias of 1.5. By testing all possible input combinations, the perceptron accurately reproduces the NAND truth table, outputting 1 for all input combinations except when both inputs are 1. This demonstrates that neural networks can effectively implement fundamental digital logic operations.

The designed neural-network-based logic gates are intended for CMOS implementation using Electric VLSI software, while circuit performance is verified through LTspice simulations. These gates also serve as the building blocks for designing a neural-network-based full adder, illustrating the potential of perceptron-based circuits in digital system design.

Conclusion

Neural network based design of logic gates and full adder are presented in this paper. All designs are based on tsmc180nm CMOS process at a supply voltage of 1.8V. Electric VLSI tools are used for making the CMOS layouts. LTspice simulations were performed on the NOT gate, two-input NAND gate and the full adder. The bias voltages are to be selected properly for the correct functioning of these circuits. For the full adder, the bias voltage for the carry side NMOS transistor is fixed at 1.8V. For the sum side NMOS transistor it is variable between 0.6V to 1.1V. Propagation delays and power dissipation varies with the bias voltage. A bias voltage of 0.85V on the sum side transistor keeps the propagation delays less than 0.5ns. The average power consumption is little over 1mW. This is much higher compared to the normal CMOS adder due to the simultaneous conduction of both NMOS and PMOS transistors under certain input conditions. The number of transistors used in the neuron adder is only 23 as compared to 36 for the CMOS adder.

References

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Copyright

Copyright © 2026 Columbus Enslen, Damu Radhakrishnan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.