Design and Implementation of a High-Speed Three-Operand Binary Adder Using Parallel Prefix Architectures

Abstract

High-speed and space-efficient arithmetic units are necessary for the hardware implementation of cryptographic algorithms to guarantee security and performance. Efficient multi-operand addition, especially three-operand binary addition, is crucial for modular operations like multiplication and exponentiation. A high-speed, low-area three-operand binary adder for cryptography and pseudorandom bit generator (PRBG) applications is presented in this study. Kogge-Stone, Han-Carlson, and Ladner-Fischer are examples of parallel prefix adders that are used to increase throughput and decrease propagation latency. For VLSI systems, heterogeneous delay-insensitive coding is used to further optimize power, area, and performance. A Carry Look-Ahead (CLA) adder, which lowers critical route delay through parallel carry generation, is added to the design to improve carry calculation. When compared to traditional designs, the suggested hybrid architecture provides increased speed and efficiency. Its usefulness for high-performance computing and digital signal processing applications is demonstrated via implementation using Xilinx Vivado.

Introduction

This study focuses on the design of high-speed, area-efficient, and low-power multi-operand adders (MOAs) for VLSI systems, particularly for applications such as multipliers, digital signal processors (DSPs), cryptography, and medical IoT devices. Since arithmetic units—especially multipliers—consume a significant portion of system power and area, optimizing multi-operand addition is essential for improving overall performance.

Background

Multi-operand adders are used to efficiently sum multiple partial products generated during multiplication. Different adder architectures offer various trade-offs:

• Ripple Carry Adder (RCA): Small area and low power but high delay.
• Carry Look-Ahead Adder (CLA): Faster operation but larger area and power consumption.
• Carry Select Adder (CSLA): Balances speed and hardware complexity.
• Carry Save Adder (CSA): Efficient for multi-operand addition by avoiding immediate carry propagation.
• Parallel Prefix Adders (PPA) (e.g., Kogge-Stone, Han-Carlson): Very fast but require more hardware.

The main challenge is reducing carry propagation delay while maintaining low area and power consumption.

Literature Review

Previous studies have explored:

• Wallace Tree Adders and compressor trees for reducing addition delay.
• Optimized CSLA designs using Binary-to-Excess-1 Converter (BEC) and Square Root CSLA to reduce area and power.
• Reversible logic for minimizing energy dissipation in low-power VLSI and quantum computing.
• Parallel prefix architectures for achieving logarithmic delay.

However, existing approaches often sacrifice one design metric (speed, area, or power) to improve another.

Existing Limitations

Current adder architectures face several trade-offs:

• RCA is compact but slow.
• CLA and PPAs are fast but consume more hardware resources.
• Wallace Tree Adders offer low delay but have irregular structures that complicate implementation.
• Carry Save Adders still require a final carry-propagation stage, limiting overall speed.

An efficient three-operand adder that simultaneously minimizes delay, area, and power remains a key research need.

Proposed Methodology

The proposed design introduces a Variable Stage Structure (VSS) combined with a hybrid Parallel Prefix Adder (PPA) architecture.

Key features include:

• Hybrid design replacing the most delay-critical stage with a Ling–Kogge-Stone Parallel Prefix Adder.
• Three-stage PPA implementation:
  1. Preprocessing
  2. Prefix carry computation
  3. Post-processing (sum generation)
• Faster carry computation using Ling equations and Kogge-Stone architecture.
• Reduced logic complexity and lower critical path delay.

Carry Select Adder Optimization

To further improve efficiency, the design incorporates:

• Binary-to-Excess-1 Converter (BEC)-based CSLA, replacing duplicate RCAs to reduce hardware and power.
• Common Boolean Logic (CBL)-based Square Root CSLA, which shares logic between carry-in cases to minimize transistor count and improve the power-delay product.

Reliability Enhancement

The proposed architecture also introduces concurrent error detection, featuring:

• Predicted parity checking.
• Dual carry outputs.
• Modified hardware blocks for complete fault detection.
• 100% fault coverage with only 10 test patterns, regardless of adder bit width.
• Improved testability (C-testability) suitable for safety-critical VLSI applications.

Conclusion

In this paper, a high-speed, area-efficient adder technique and its VLSI architecture are proposed to perform the three-operand binary addition for efficient computation of modular arithmetic used in cryptography and PRBG applications. The proposed three-operand adder technique is a parallel prefix adder that uses four-stage structures to compute the addition of three input operands. The novelty of this proposed architecture is the reduction of delay and area in the prefix computation stages in PG logic and bit-addition logic, which leads to an overall reduction in area and delay. For a fair comparison, the concept of a hybrid Han-Carlson two-operand adder is extended to develop a hybrid Han-Carlson three-operand adder (HHC3A) topology. The same coding style adopted in the proposed adder architecture is extended to implement the hybrid Han-Carlson three-operand adder, Kogge Stone, using Verilog HDL. Further, all these designs are synthesized using the commercially available Spartan 3 technology library to obtain the core area and delay timing. Application-wise, we implemented our adder in the adder part of an FIR filter for further efficiency in the field of area and delay. Concluding that our adder was comparatively better than other adders by considering both the area and delay.

References

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Copyright

Copyright © 2026 S Aparna, C Padma. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.