An Efficient Approximate Compressor Architecture for Balanced Error Accumulation in MAC Units

Abstract

Designing energy-efficient and high-performance arithmetic hardware remains a major challenge for modern computing systems, particularly for the multipliers and compressors that dominate multiply–accumulate (MAC) workloads. This paper presents an efficient approximate compressor architecture designed to achieve balanced error accumulation in MAC units used for error-tolerant applications such as image processing and machine learning (ML). The proposed architecture selectively simplifies the compressor stages that reduce partial products of least numerical significance, while preserving exact computation for the bits that dominate accuracy, so that approximation error accumulates in a controlled and balanced manner rather than growing unpredictably across operand widths. Building on this compressor, a configurable multiply–accumulate (MAC) unit for ML hardware is developed, capable of switching between an exact mode and 2-bit and 4-bit approximate compression modes at runtime according to instantaneous power and accuracy requirements. A modified, error-compensated activation function is further proposed to offset the systematic bias introduced by the approximate compressor at the neuron output. The proposed architecture is implemented in SystemVerilog and synthesized with Synopsys Design Compiler for UMC 90 nm CMOS technology, with functional validation on FPGA platforms. A Gaussian blur filter is used to evaluate the compressor in an image-processing pipeline, while a multilayer perceptron (MLP) trained on standard ML datasets evaluates the configurable MAC unit and the compensated activation function. Experimental results show that the proposed approximate compressor architecture achieves substantial reductions in power, area, and energy per operation relative to an exact Wallace-tree baseline, while keeping error metrics such as NMED, MRED, and ER low and well balanced across configurations, making it a strong candidate for energy-constrained, error-tolerant computing systems.

Introduction

This paper presents a configurable approximate compressor architecture for energy-efficient multiplication in machine learning (ML) and edge computing systems. Unlike conventional approximate arithmetic circuits with fixed accuracy, the proposed design dynamically switches between exact, 2-bit approximate, and 4-bit approximate compressor modes to balance power consumption and computational accuracy based on available energy. The architecture targets multiplier compressor trees, where reducing switching activity and hardware complexity significantly lowers power, delay, and silicon area while maintaining acceptable accuracy for error-tolerant applications such as image processing and neural network inference.

The proposed architecture is implemented using SystemVerilog and evaluated with Xilinx Vivado and Synopsys Design Compiler in UMC 90 nm CMOS technology. It uses a configurable Wallace-tree multiplier, a configurable MAC unit, and a modified activation function that compensates for approximation errors using a compensation factor derived from the Normalized Mean Error Distance (NMED). Instead of duplicating hardware, the design reuses the same adder cells across different operating modes, requiring only minimal additional control logic.

Experimental results show that the 4-bit approximate compressor achieves significant reductions in power, area, latency, and energy consumption while introducing only small, balanced errors. Tests on image processing and neural network applications demonstrate minimal degradation in image quality and classification accuracy. Compared with previous approximate multiplier and compressor designs, the proposed architecture provides higher energy savings with lower and more predictable error, making it well suited for resource-constrained AI accelerators, edge devices, and energy-harvesting systems where runtime adaptability and efficiency are essential.

Conclusion

This work has presented an efficient approximate compressor architecture for balanced error accumulation in MAC units, targeting energy-constrained, error-tolerant applications. Approximate computing offers design techniques at many abstraction levels for building on-chip systems that are efficient in both energy and performance, and approximate compressors — a key subfield of approximate arithmetic — have drawn considerable attention in the literature. The central contribution of this work is a configurable compressor structure whose approximation level can be tuned on the fly through logic-compression control, so that a single set of adder cells serves the exact mode as well as multiple approximate compression modes. An energy-aware configuration strategy selects the appropriate compressor mode based on available energy, and the results show that the design executes reliably at runtime even under highly variable energy conditions, while reusing the same adder cells across configurations saves silicon area and leakage energy. Building on the proposed compressor, a configurable MAC unit was designed for power-adaptive ML hardware, and its configuration is optimized at runtime using the same energy-aware strategy. The resulting MAC unit was deployed within neuron modules of an ML system, and a model-driven, power-adaptive neuron architecture was constructed around it. Despite significant reductions in energy use and area, the resulting drop in output quality was minimal. Finally, a customizable, error-compensated activation function was proposed to further reduce the impact of the approximate compressor on prediction accuracy. Together, these three contributions — the approximate compressor, the configurable MAC unit, and the compensated activation function — allow energy-adaptive neural-network hardware to realize substantial power and area savings with negligible degradation in output quality. Future work will extend the proposed approximate compressor architecture to larger operand sizes, such as 16×16 and 32×32 multipliers, and integrate the resulting MAC units into more complex deep-learning accelerators. Another promising direction is to co-optimize the approximate compressor hardware with quantization-aware training so that the neural network can explicitly adapt its weights to the characteristics of the underlying arithmetic units. Finally, implementing and validating the architecture on more advanced technology nodes and additional FPGA platforms will provide further insight into its scalability and practical deployment in real-world edge-AI systems.

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Copyright

Copyright © 2026 Tirupati Yaswanth, Dr. Suresh Babu Potladurty. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.