Design of the Efficient Leading Zero Counter

Abstract

A Leading Zero Counter(LZC) is a digital circuit that determines the number of leading zeros in a binary number, and its design considerations include speed, area, and power consumption.The working of a 64-bit LZC is studied in this paper.The functionality of a 64-bit leading zero counter is investigated through a hierarchical design approach. Starting from a basic 2-bit configuration, the counter\'s underlying mechanics areanalysed and subsequently scaled up to accommodate 64-bit operations.In this paper basic gates such as AND gate, OR gate and inverter are used for implementing leading zero counter. Boolean equations are formed from previously proposedarchitectures and after simplifying that Boolean expression a new architecture for LZC unit is formed.Further calculation can be performed for a 128-bit leading zero counter. Performance and analysis of the 64-bit LZC can be conducted using this method, and the Xilinx Vivado design suite is utilized to simulate and synthesize the 64-bit leading zero counter.

Introduction

Overview

A Leading Zero Counter (LZC) is a digital circuit that determines the number of consecutive zeros at the beginning of a binary number. It is vital in high-performance computing for applications such as floating-point arithmetic, cryptography, and digital signal processing. This study presents the design and implementation of a 64-bit LZC, capable of efficiently counting leading zeros in large binary numbers, using hierarchical and hardware-efficient architecture.

Key Features of the 64-bit LZC

• Accepts a 64-bit binary input and outputs a 7-bit result: a flag (V) for all-zero detection and a 6-bit count (Z) of leading zeros.

• Built using a recursive, modular structure:

  • Combines two 32-bit LZCs

  • Each 32-bit LZC is composed of two 16-bit LZCs, and so on down to 2-bit modules

• Supports parallel processing and low-latency operation.

• Offers high scalability and compatibility with modern 64-bit computing systems.

Literature Survey Insights

• Multiple prior works have developed LZCs for 8-bit to 64-bit operations, primarily on FPGAs.

• Design approaches vary from ASIC-based logic to probabilistic and approximate techniques for better energy efficiency.

• Some methods use direct logic, while others rely on hierarchical composition.

• Optimization efforts focus on reducing LUTs (Look-Up Tables), slices, power consumption, and delay, making them suitable for low-power and real-time systems like IoT and edge AI.

Proposed Design Methodology

• Stepwise modular construction:

  • Start with a 2-bit LZC (2 inputs, 2 outputs: V and Z)

  • Extend to 4-bit, 8-bit, 16-bit, 32-bit, and finally 64-bit by combining lower-bit modules

• Logic gates and equations are used to compute the overflow flag (V) and zero count (Z).

• RTL (Register Transfer Level) design and waveform simulations confirm functionality at each level.

Results and Performance

• RTL schematics and waveform outputs for each version (2-bit to 64-bit) confirm the design’s correctness.

• Comparative analysis table shows that the proposed design:

  • Consumes the least power across all bit-widths

  • Uses fewer LUTs and slices

  • Has competitive delay

  • Achieves lowest Power-Delay Area Product (PDAP) in most cases, especially at 64-bit

Conclusion

In this paper, a 64-bit Leading Zero Counter (LZC) was designed using a hierarchical approach, starting from a 2-bit configuration and expanding to handle 64-bit numbers. Basic gates such as AND, OR, and inverters were used to form and simplify Boolean expressions, leading to an optimized LZC architecture. The design was synthesized and analyzed using Xilinx Vivado, where reports on area, power, and timing were obtained, highlighting the trade-offs in resource utilization and performance. This design serves as a foundation for extending to larger bit-width counters, like 128-bit LZC, and can be applied in fields such as digital signal processing, high-performance computing, and cryptography, where efficient leading zero detection is essential. Future work could focus on further power optimization and integration into larger systems for more complex applications.

References

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Copyright

Copyright © 2025 M. Deepika Krishna, G. Sowjanya , K. K. V. Sri Vihar , J. N. Bhanu Prakash, K. Bhanu Sandeep. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.