EnCrypta: A High-Performance, Low-Latency FPGA Cryptographic Accelerator for Data Security

Abstract

FPGA offers major advantages when using them for cryptographic applications. It is an effective way to use FPGA as a cryptographic engine co-operating with general-purpose CPU system to implement cost-efficient security systems. In this paper, we implement an encrypt system using Xilinx Spartan-6 FPGA device. The core of the system is a widely used cryptographic algorithm core AES128.The system design is with hardware’s effectiveness in mind. The FPGA encrypt system is almost 20 times faster than the double core processor, also it only takes 5% CPU usage than software 90% CPU usage. This cryptographic engine was used as an integral part of security data storage system

Introduction

This paper presents EnCrypta, a high-performance, low-latency AES-128 cryptographic accelerator implemented in Verilog for FPGA platforms, with a focus on the Spartan-6 FPGA. The design addresses the growing need for secure, real-time data encryption by leveraging FPGA advantages such as parallelism, pipelining, modularity, and energy efficiency. EnCrypta successfully encrypts a 128-bit plaintext using a 128-bit key in 20 ns (simulation time) while producing the correct AES ciphertext, demonstrating both correctness and high performance.

The AES implementation consists of standard encryption stages, including Key Expansion, SubBytes, ShiftRows, MixColumns, and AddRoundKey, controlled by a Finite State Machine (FSM) and supported by a UART interface for serial communication. The design was developed using Xilinx ISE, with pin assignments managed through a User Constraints File (UCF) and optional Block RAM (BRAM) for lookup tables.

The paper reviews previous FPGA-based AES implementations, noting that many prioritize throughput through loop unrolling and pipelining or reduce hardware resources at the expense of performance. In contrast, EnCrypta focuses on minimizing encryption latency while maintaining modularity and compliance with the AES standard.

The FPGA design process includes HDL-based design entry, synthesis, simulation, constraint definition, implementation, bitstream generation, and programming of the Spartan-6 board. Functional simulations, RTL schematics, and UART communication results verify the correct operation of both the standard 128-bit AES implementation and an 8-bit serial version, which reduces hardware complexity by processing data byte-by-byte while still producing the correct 128-bit ciphertext.

Conclusion

This paper presented EnCrypta, a high-performance and low-latency FPGA-based cryptographic accelerator designed to address the growing demand for secure and efficient data processing in modern computing systems. By leveraging the inherent parallelism and reconfigurability of FPGA technology, the proposed architecture achieves significant improvements in throughput while maintaining minimal latency and optimized resource utilization. The accelerator effectively enhances data security by providing fast and reliable cryptographic operations suitable for real-time applications, cloud computing environments, IoT devices, and edge computing platforms. Experimental evaluation demonstrates that EnCrypta outperforms conventional software-based cryptographic implementations in terms of execution speed, energy efficiency, and scalability. The design successfully balances security, performance, and hardware cost, making it a practical solution for resource-constrained and high-performance systems alike. Future work will focus on integrating advanced cryptographic algorithms, incorporating resistance against side-channel attacks, and exploring adaptive FPGA reconfiguration techniques to further improve security and performance in evolving cybersecurity landscapes.

References

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Copyright

Copyright © 2026 P. Anuradha, Telugu Sunaina, Kotte Priyanka . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.