Design and Implementation of a Power-Efficient 32-bit MAC Unit Using Vedic Multiplier and 64-bit CLA with Clock Gating for FPGA-Based Applications

Abstract

This study presents development and implementation of a power-efficient architecture of a 32-bit MAC Unit built with Verilog HDL for FPGA applications. This architecture also connects a Vedic multiplier to boost multiplication, along with a architecture of 64-bit CLA and64-bitMACUnitaccumulatortofacilitaterapidaccumulation withreducedpropagation delay. To reduce power, RTL clock gating is used to eliminate unnecessary switching activities. To check correctness and performance of the proposed ISUM design, we perform simulation and verification in Xilinx Vivado. Post-synthesis verification results onimportant parameters such as timing, resource usage and dynamic power are presented and revealsignificantimprovementsovertraditionalMACarchitectures.Furthermore,thedesign is scalable, allowing higher bit width computations to be performed with very few modifications. The architecture is a computing element with better performance in terms of performance and energy codes, a comparative study with the correct MAC units will show thattheMACprocessingelementsarethemostsuitableunitsforhigh-performanceDSPand AI-drivenFPGAs.

Introduction

Objective

The paper proposes a low-power, high-speed MAC (Multiply and Accumulate) unit for Digital Signal Processing (DSP) applications, addressing the drawbacks of classical MAC architectures like high power consumption and latency.

Key Innovations

1. Vedic Multiplier (Urdhva Tiryagbhyam Method)

   • A 32×32 multiplier based on Vedic mathematics that performs faster by minimizing partial products.

   • Enhances parallelism, reduces energy usage, and lowers signal delay.

   • Ideal for real-time, low-power applications like IoT and embedded systems.

2. 64-bit Carry Look-Ahead Adder (CLA)

   • Used to accelerate addition operations by minimizing carry propagation delay.

   • Supports high-speed arithmetic with better power efficiency and scalability.

3. 64-bit Accumulator

   • Stores results across cycles, enabling fast and precise accumulation in iterative DSP processes.

4. Clock Gating

   • Reduces dynamic power consumption by disabling inactive clock segments.

   • Power savings up to 35% in some implementations.

5. Pipelining

   • Employed to improve throughput and minimize latency across the MAC architecture.

Implementation

• Developed using Verilog HDL, synthesized on Xilinx Vivado and FPGA platforms.

• Modular and scalable design enables expansion to higher bit-widths (64-bit or 128-bit).

• Incorporates register-transfer level (RTL) modeling and logic synthesis for efficiency.

Performance Evaluation

• Resource Utilization (Xilinx FPGA):

  • LUTs: 1.63%, Flip-Flops: 0.02%, I/Os: 32.75%, BUFGs: 3.13%

• Delay Comparisons:

  • Ripple Carry Adder: 55 ns

  • Carry Look-Ahead Adder: 15 ns

  • Carry Save Adder: 20 ns

• Power Analysis:

  • Total power: 152.06W

    • 99% dynamic power (mainly from I/O and logic)

    • 1% static power

Literature Insights

• Vedic multipliers and clock gating are proven techniques for power-efficient design.

• CLA enhances speed in multi-bit operations.

• Previous studies validated energy savings using reversible logic and Vedic methods in MAC units.

Future Scope

• Use of Dynamic Voltage and Frequency Scaling (DVFS) and MTCMOS to further reduce power.

• Extension to 64-bit/128-bit MAC units for more complex DSP and ML tasks.

• Exploration of emerging technologies (e.g., memristors, quantum-dot logic).

• Adaptation for edge computing and mobile AI inference.

• Migration to advanced nodes (7nm, 5nm) for improved power-performance ratio.

Conclusion

This research aims to develop an optimized, energy-efficient 32-bit MAC unit with a Multiplier Using Vedic Mathematics and a 64-bit CLA (Carry Look-Ahead Adder) using clock gating methodologies. New architecture provides the design simplicity at the higher computationspeed withlow propagationdelayandpowerconsumptionfor high performance applications. Through clock gating, the design reduces dynamic power consumption by inhibiting clock signals within idle areas, enhancing system-wide energy efficiency. Designed based on Verilog HDL and synthesized in Xilinx Vivado, the design proves to feature significant speed boosts at reduced power consumption relative to standard MAC blocks. This architecture offers a scalable and high-performance solution for contemporary computing systems, with potential for additional optimization via pipelining and sophisticated power management methods.

References

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Copyright

Copyright © 2025 K. Manisha, V. Sai Sagar, K. Omkiran, P. Naga Chirudeep, G. Prem Sai. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.