Design of a Three-Operand Binary Adder Using Parallel Prefix Architectures

Abstract

High-speed arithmetic operations are fundamental to modern digital systems, where multi-operand addition frequently determines the critical timing path. Conventional cascaded two-operand adders result in sequential carry propagation and increased latency. This paper presents an FPGA implementation employing carry computation to enhance timing performance. The proposed architecture decouples operand compression from carry resolution, thereby reducing critical path delay. Kogge–Stone, Han–Carlson, and Ladner–Fischer prefix structures are implemented in Verilog HDL and synthesized on an Artix-7 FPGA platform. Experimental results indicate that structured prefix networks improve computational efficiency while providing scalable trade-offs among delay, area, and power for high-throughput arithmetic systems.

Introduction

Arithmetic circuits, particularly adders, are fundamental to digital systems like processors, ALUs, and signal-processing units. Binary addition is frequently executed and often on the critical path, making low-latency, high-throughput adder design a key focus in VLSI and FPGA-based systems. Traditional multi-operand addition is performed using cascaded two-operand adders, which sequentially propagate carries, increasing critical path delay and limiting performance for wide-word operations.

To overcome this, parallel prefix adders compute carry signals hierarchically using associative operations, reducing carry propagation depth to logarithmic with respect to operand width. Well-known topologies—Kogge–Stone, Han–Carlson, and Ladner–Fischer—balance speed, wiring complexity, and fan-out in two-operand addition. However, structured three-operand addition with FPGA validation has been less explored.

The proposed methodology introduces a three-operand binary adder with:

1. Operand Compression Stage: Compresses three input bits at each position into intermediate sum (Si′ = Ai ⊕ Bi ⊕ Ci) and carry (Ci′ = AiBi + BiCi + AiCi) signals, enabling independent bit-level processing.

2. Parallel Prefix Carry Computation: Global carries are resolved using hierarchical prefix networks (Gi = Ci′, Pi = Si′) and an associative prefix operator (Gk, Pk) ? (Gj, Pj) = (Gk + PkGj, PkPj), achieving logarithmic carry resolution depth.

3. Final Sum Generation: Combines intermediate sums with resolved carries (Si = Si′ ⊕ Ci) to produce the final result.

The design integrates multiple prefix topologies for comparison:

• Kogge–Stone: Minimal logic depth, high interconnect density.

• Han–Carlson: Hybrid approach balancing depth and wiring.

• Ladner–Fischer: Flexible construction with controlled fan-out, reduced routing congestion.

FPGA Implementation:

• Modular Verilog HDL design targeting Artix-7 FPGA.

• Tested for 16-bit and 32-bit operands with post-synthesis evaluation of LUT/FF usage, critical path delay, maximum frequency, and power consumption.

• The integrated compression + prefix architecture eliminates sequential carry dependency, providing scalable, high-speed three-operand addition suitable for performance-critical digital arithmetic systems.

Conclusion

This work presented the design and FPGA implementation of a structured three-operand binary adder based on parallel prefix carry computation. The proposed architecture integrates bit-level operand compression with hierarchical carry resolution, thereby eliminating sequential carry dependency present in conventional cascaded designs. Three established prefix topologies—Kogge–Stone, Han–Carlson, and Ladner–Fischer—were implemented and evaluated on an Artix-7 FPGA platform for 16-bit and 32-bit configurations. Experimental results demonstrate that the Kogge–Stone architecture achieves the lowest propagation delay, making it suitable for high-performance arithmetic applications. The Han–Carlson topology provides a balanced trade-off among area, delay, and power consumption, while the Ladner–Fischer structure offers moderate area efficiency with comparatively higher delay at larger operand widths. The observed timing trends confirm the logarithmic carry resolution property of prefix-based architectures, ensuring controlled delay growth with increasing word length. Overall, the integration of three-operand compression with structured parallel prefix networks enables scalable and efficient multi-operand addition on FPGA platforms. The proposed framework offers a practical solution for high-throughput arithmetic systems requiring improved timing performance and architectural flexibility.

References

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Copyright

Copyright © 2026 Dr. T. Madhavi Kumari, Chinnapally Muni Akhila. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.