UVM Based RISC-V Verification Using Arduino Uno

Abstract

This paper presents the design and implementation of a Universal Verification Methodology (UVM) based verification environment for a RISC-V processor core integrated with an Arduino Uno interface. The work demonstrates a practical approach to processor verification where testbench results are interfaced through Arduino for display and serial communication. The SystemVerilog-based UVM environment automates constrained random testing, coverage analysis, and assertion-based verification. Results indicate over 90% instruction coverage, validating the processor’s functional correctness and proving UVM’s efficiency for academic and industrial verification projects.

Introduction

The paper presents a UVM-based verification framework for a 32-bit RISC-V processor core, enhanced with an Arduino Uno for real-time output visualization and serial communication. As verification consumes about 70% of total design time in processor development, structured methodologies like Universal Verification Methodology (UVM) are crucial.

Literature Review

Previous works—such as RISCV-DV, riscv-formal, and OpenHW CORE-V—focus on simulation and formal verification of RISC-V processors. However, few integrate microcontrollers for physical or educational demonstrations, highlighting the novelty of this approach.

Methodology

The system is divided into:

• Design Domain: RISC-V core RTL, memory, and interfaces.

• Verification Domain: UVM components (sequencer, driver, monitor, scoreboard, and coverage collector).
  The testbench uses constrained-random instruction sequences, compares results with a golden model, and outputs verification results via Arduino Uno.

Results

Simulations using Synopsys VCS achieved over 90% functional coverage, validating the processor’s correctness. QuestaSim waveforms confirmed proper instruction execution and register updates. The Arduino Uno provided real-time visualization, making the setup useful for educational and experimental applications.

Conclusion

This paper demonstrated a complete UVM-based verification environment for a RISC-V processor core integrated with Arduino Uno for result visualization. The developed testbench achieved high coverage and proved effective in detecting design bugs. The methodology can be extended to verify advanced RISC-V extensions and implement hardware testing using FPGA platforms. Future work includes integrating formal verification and machine learning-based test generation for intelligent verification flows.

References

[1] Chips Alliance, “RISCV-DV: Open-source Random Instruction Generator for RISC-V Processor Verification,” GitHub, 2024. [2] YosysHQ, “riscv-formal: Formal Verification Framework for RISC-V Cores,” ReadTheDocs, 2024. [3] OpenHW Group, “CORE-V Verification Environment (CV32E40P),” OpenHW Documentation, 2024. [4] Synopsys Inc., “VCS User Guide: UVM Simulation and Verification,” Synopsys, 2024. [5] M. Zachariášová et al., “UVM-Based Verification of a RISC-V Processor Core,” DVCon Europe, 2023.

Copyright

Copyright © 2025 Arya S. Kutwal, Pranav D. Yadav, Ajit A. Ware. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.