This work focuses on the implementation of an efficient adaptive noise cancellation system using FPGA technology based on LMS (Least Mean Squares) and LLMS (Leaky LMS) algorithms. The aim is to enhance real-time audio signal processing by mitigating unwanted noise effectively. Initially, MATLAB was used to process noisy and clean audio signals, which were then simulated using Verilog in Xilinx ISE 14.7. The LMS and LLMS algorithms were implemented and compared for their performance in noise cancellation. The LLMS algorithm demonstrated superior performance, achieving significant improvements in Signal-to-Noise Ratio (SNR), Peak Signal-to-Noise Ratio (PSNR), Mean Squared Error (MSE), and stability compared to the traditional LMS approach. This project demonstrates the practical applicability of LLMS-based ANC systems for embedded, low-power, real-time noise cancellation applications. Future work includes deploying the system on physical FPGA boards, optimizing resource usage further, and testing under dynamic noise environments to validate real-world performance.
Introduction
In modern urban environments, noise pollution from electronic devices and industrial growth impacts quality of life and critical communications. Adaptive Noise Cancellation (ANC) using adaptive filters, especially the Least Mean Square (LMS) algorithm, is a key technique to suppress unwanted noise. However, LMS faces challenges like coefficient drift and stability issues in real-time, low signal-to-noise ratio (SNR) conditions. The Leaky LMS (LLMS) algorithm improves on LMS by adding a leakage factor, enhancing stability and convergence.
While LMS and LLMS are well-studied in software (e.g., MATLAB), implementing them on hardware platforms like Field Programmable Gate Arrays (FPGAs) brings advantages such as parallelism, low latency, and real-time processing. Despite these benefits, few studies have compared LMS and LLMS implemented via hardware description languages (e.g., Verilog) on FPGAs.
This work develops an FPGA-based ANC system using both LMS and LLMS algorithms, simulated and implemented with tools like Xilinx ISE, MATLAB, and Vivado. The design includes noisy input, adaptive FIR filtering, error calculation, and output signal generation. Performance metrics such as Mean Squared Error (MSE), Signal-to-Noise Ratio (SNR), and Peak SNR (PSNR) were used to evaluate both algorithms under identical noisy conditions.
Key Findings:
LLMS consistently outperforms LMS in terms of lower error (MSE, NMSE), higher PSNR, and improved output SNR.
LLMS provides around 43% less error and nearly 20% better noise cancellation than LMS.
The correlation between the desired and output signals is higher for LLMS, indicating better signal tracking.
LLMS shows enhanced stability, robustness, and noise suppression capabilities on FPGA implementations.
Conclusion
The LLMS algorithm achieved a reduction in mean squared error by a factor of 0.43 compared to the standard LMS algorithm, and it provided an improvement in signal-to-noise ratio that was approximately 1.2 times higher. Additionally, LLMS exhibited better convergence speed and greater stability. These results confirm that LLMS is more robust, particularly in scenarios involving fluctuating noise conditions and long-duration filtering requirements.
Quantitative evaluation confirmed significant performance gains:
1) SNR improvement: 15.82 dB (LLMS) vs. 13.22 dB (LMS)
2) Convergence: LLMS showed smoother and faster convergence in waveform analysis
3) Resource Efficiency: Simulations suggested that LLMS could be implemented without exceeding typical resource constraints on mid-range FPGA boards
The Verilog design was carefully written with hardware efficiency in mind, using fixed-point arithmetic to reduce computational load. Despite the added complexity of LLMS, optimizations ensured that logic usage remained within acceptable bounds, and simulation timings were well within real-time constraints. No significant performance was sacrificed to achieve this optimization
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