Advanced Ternary Addition Circuits Leveraging Carbon Nanotube Field-Effect Transistors

Abstract

This work introduces new ternary addition circuits realized in terms of \"carbon nanotube field-effect transistors\" (CNFETs). These designs take advantage of the characteristic features of CNFETs to gain significant improvements in device numbers, power dissipation, and computation time over traditional CMOS-based ternary adders. Three different CNFET-based ternary adder architectures are introduced: a basic design, an optimized design leveraging the multiple threshold voltages and the ability to realize complex ternary functions using fewer transistors in CNFETs, and a high-performance design employing a novel ternary logic family called CNFET Ternary Logic(CTL).The proposed designs are extensively simulated and analyzed using a 32nm CNFET SPICE model. The results demonstrate up to a 58% reduction in transistor count, 68% lower power consumption, and 1.8X faster computation than state-of-the-art CMOS ternary adders. The pros and cons of CNFET based multi valued logic (MVL) design are discussed and could prove helpful in future research in this domain. It provides a ray of hope that CNFET technology has the potential to create performance and energy-efficient MVL circuits, which in turn facilitates the creation of advanced ternary arithmetic units and computing systems.

Introduction

As CMOS technology approaches its physical and performance limits at the nanoscale, new device paradigms are needed. One promising alternative is the Carbon Nanotube Field-Effect Transistor (CNFET), which offers:

• High carrier mobility, large drive current, and low leakage.

• Support for multiple threshold voltages, making it ideal for Multi-Valued Logic (MVL) systems like ternary logic (radix-3).

Ternary logic (with values 0, 1, 2) can encode more information per digit, reduce wiring complexity, and improve arithmetic efficiency over traditional binary logic. However, prior research has focused mainly on basic gates, with little attention to ternary arithmetic circuits like adders.

Research Contributions

This work proposes and evaluates three CNFET-based ternary adder designs:

1. Basic Design: Built using CNFET implementations of ternary half-adder (THA) and full-adder (TFA) with NAND and NOR gates.

2. Optimized Design: Uses multiple threshold CNFETs to reduce transistor count and energy consumption.

3. High-Performance Design: Employs a new CNFET Ternary Logic (CTL) family for minimal delay and maximal performance.

The study includes:

• SPICE simulations (32nm CNFET model) to measure delay, power, and area.

• Comparative analysis with state-of-the-art CMOS-based ternary adders, showing superior performance in all metrics.

Technical Highlights

Advantages of CNFETs:

• Ballistic transport → ultra-fast switching

• Low leakage → high energy efficiency

• High thermal conductivity → better heat management

• Customizable threshold voltages → ideal for MVL systems

Ternary Logic Benefits:

• Reduces chip area and interconnect complexity

• Enables efficient arithmetic and signal processing

• Supports applications like ternary filters and neural networks

Adder Designs:

• Basic Adder: Uses standard ternary gates; functional but not optimized.

• Optimized Adder: Fewer transistors, lower power via advanced CNFET properties.

• High-Performance Adder: Leverages CTL gates (CTL Inverter, CTLNAND, CTLNOR) for speed and compactness.

Conclusion

This paper presented novel CNFET-based ternary adder designs that leverage the unique properties of CNFET to achieve superior performance and energy efficiency. Three innovative designs were introduced: a basic, optimized, and high-performance design featuring the novel CNFET Ternary Logic (CTL) family. Extensive SPICE simulations using a 32nm CNFET model demonstrated remarkable improvements over CMOS ternary adders. The optimized design achieved a 58% reduction in transistor count, 62% lower power consumption, and 1.6X faster operation. The high-performance design with CTL gates showed even better results, witha52%reductionintransistorcount,68%lower power consumption, and 1.8X faster operation than CMOS implementations. The development of the CTL family represents a significant advancement in CNFET-based MVL circuits, demonstrating the potential for high-performance, energy-efficient ternary logic implementations. Future research directions include expanding the CTL family, developing synthesis tools for CNFET-based MVL design, and advancing manufacturing techniques. This work contributes significantly to CNFET- based MVL design, paving the way for future developments in high-performance, energy-efficient ternary arithmetic circuits.

References

[1] J.M.Veendrick, H. (2017) “Effects of Scaling on MOS IC Design andConsequences for the Roadmap” In: Nanometer CMOS ICs. Springer, Cham.https://doi.org/10.1007/978-3-319-47597-4_11 [2] Liu, S et. al. (2024) “High-Performance Carbon Nanotubeoptoelectronictransistorwithoptimizedprocessfor3Dcommunicationcircuit applications” IEEE Journal of the Electron Devices Society, 12,889–897.https://doi.org/10.1109/jeds.2024.3465669 [3] Prakash, P., Sundaram, K. M., & Bennet, M. A. (2018). A review oncarbonnanotubefieldeffecttransistors(CNTFETs)forultra-lowpowerapplications.RenewableandSustainableEnergyReviews,89,194–203.https://doi.org/10.1016/j.rser.2018.03.021 [4] Chen, Z., et. al.(2024) “Progress on a Carbon Nanotube Field-EffectTransistorIntegratedCircuit:stateoftheart,challenges,andevolution” Micromachines,15(7),817.https://doi.org/10.3390/mi15070817 [5] Firouzi, S., et. al.(2019b) “High performance, variation-tolerantCNFETternaryfulladderaprocess,voltage,andtemperaturevariation-resilient design” Computers & Electrical Engineering, 77, 205–216.https://doi.org/10.1016/j.compeleceng.2019.05.018 [6] Zahoor, F et. al. (2024) “Design Implementations of Ternary LogicSystems: A Critical Review” Results in Engineering, 23, 102761.https://doi.org/10.1016/j.rineng.2024.10276 [7] Vijay, M.,et. al. (2024) “Enhancing high-speed digital systems: MVLcircuit design with CNTFET and RRAM” Journal of King SaudUniversity - Computer and Information Sciences, 36(4), 102033.https://doi.org/10.1016/j.jksuci.2024.102033 [8] Gadgil, S., & Vudadha, C. (2022). “Novel design methodologies forCNFET-Based Ternary Sequential Logic circuits”. IEEE Transactionson Nanotechnology, 21, 289–298.https://doi.org/10.1109/tnano.2022.3184759 [9] S. Tabrizchi, F. Sharifi, M. H. Moaiyeri, and K. Navi, \"High-efficientcarbonnanotubeFET-basedternarycircuitsbyadaptivebodybiasing,\"IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66,no. 12, pp. 4931-4942, Dec. 2019. [10] Sethi, D., Kaur, M. & Singh, G. Design and performance analysis of aCNFET-based TCAM cell with dual-chirality selection. J ComputElectron16,106–114(2017).https://doi.org/10.1007/s10825-017-0952-4 [11] Gupta, N., Dixit,A. (2021). Carbon Nanotube Field-Effect Transistors(CNFETs): Structure, Fabrication, Modeling, and Performance. In:Hazra, A., Goswami, R. (eds) Carbon Nanomaterial Electronics:Devices and Applications. Advances in Sustainability Science andTechnology. Springer, Singapore. https://doi.org/10.1007/978-981-16-1052-3_9 [12] Sridharan, K., Srinivasu, B., & Pudi, V. (2020). Low-complexityarithmetic circuit design in carbon nanotube field effect transistortechnology. In Carbon nanostructures. https://doi.org/10.1007/978-3-030-50699-5

Copyright

Copyright © 2025 Anjali Pathak, Nidhi Sharma, Kanika Jindal. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.