This paper presents a comparative analysis of fault behaviour in conventional and fault-tolerant five-level Neutral-Point Clamped (NPC) inverters. While conventional multilevel inverter architectures are known for their ability to lower Total Harmonic Distortion (THD) and reduce the need for bulky filters, they often encounter reliability concerns due to a higher component count and challenges in maintaining capacitor voltage balance. In contrast, fault-tolerant inverter designs are developed to improve system dependability by minimizing the impact of faults in power sources or switching devices, often through optimized switching strategies that require minimal circuit modifications. Moreover, decreasing the number of active switching devices not only improves overall system efficiency but also enhances its ability to withstand faults, making the setup more robust and reliable.This work investigates the fault performance of both conventional and fault-tolerant five-level NPC inverters under varied operational scenarios. The analysis is performed using MATLAB/Simulink simulations, with the outcomes validating the improved reliability offered by fault-tolerant configurations.
Introduction
Multi-Level Inverters (MLIs), particularly the five-level Neutral Point Clamped (NPC) topology, are widely used in power electronics for their ability to generate high-quality voltage waveforms with low harmonic distortion. The five-level NPC inverter improves upon the traditional three-level version by providing more voltage steps, which reduces switching stress, lowers Total Harmonic Distortion (THD), and smooths output waveforms.
However, NPC inverters are vulnerable to faults like open-circuit (OC) and short-circuit (SC) failures in switching devices (IGBTs, MOSFETs). Such faults cause voltage imbalance, increased harmonics, instability, and can degrade system performance or cause shutdowns.
To enhance reliability, fault-tolerant NPC inverters incorporate redundant switches, bypass paths, and adaptive control strategies to maintain operation during faults. These designs allow the inverter to reconfigure its switching patterns to bypass faulty components, often operating at fewer voltage levels (e.g., switching from five-level to three-level operation) while still providing stable output. This improves system resilience but can increase design complexity and cost.
Literature Survey
The traditional five-level NPC inverter uses multiple switches, clamping diodes, and DC-link capacitors to achieve five discrete voltage levels (+Vdc/2, +Vdc/4, 0, -Vdc/4, -Vdc/2), reducing THD and voltage stress.
Limitations include voltage imbalance across capacitors, complexity, and higher failure risk in semiconductor switches.
Fault-tolerant designs dynamically adjust switching to maintain output voltage and system stability during component faults, though at the expense of increased complexity and cost.
Example fault-tolerant topology uses two DC sources, diodes, and unidirectional switches to switch to a lower-level operation mode and maintain voltage using a transformer.
Simulation Results (using MATLAB)
Traditional five-level NPC inverter:
Without fault: Produces smooth output voltage with THD ~20.32%.
With fault (e.g., IGBT open switch): Output voltage waveform becomes distorted, THD increases to ~36.87%, showing degradation in power quality.
Fault-tolerant five-level NPC inverter:
Without fault: Output voltage and THD (~20.3%) similar to traditional inverter.
With fault (e.g., DC source failure): Maintains more stable output waveform and better power quality compared to traditional inverter under fault conditions.
Conclusion
The results indicate that while conventional NPC inverters suffer from significant performance degradation in the presence of faults, the proposed fault-tolerant topology effectively mitigates these issues by redistributing voltage levels and maintaining operational stabilityBoth simulation and experimental studies show that the fault-tolerant NPC inverter offers better reliability, lowerTHD, and stronger performance in the presence of a faults. These improvements make it a promising option for demanding applications like renewable energy systems and industrial motor drives, where consistent and reliable operation is crucial.
References
[1] S. Ahmadi, P. Poure, S. Saadate, and D. A. Khaburi, “Fault tolerance analysis of five-level neutral-point-clamped inverters under clamping diode open-circuit failure,” Electronics, vol. 11, no. 9, p. 1461, 2022.
[2] P. Ba, K. Suresh, and E. Parimalasundar, “Fault analysis in the 5-level multilevel NCA DC–AC converter,” Automatika, vol. 64, no. 3, pp. 606–612, 2023.
[3] M. Jalhotra, L. K. Sahu, S. P. Gautam, and S. Gupta, “Reliability and energy sharing analysis of a fault-tolerant multilevel inverter topology,” IET Power Electronics, vol. 12, no. 4, pp. 819–828, 2019.
[4] N. K. Dewangan, T. K. Tailor, R. Agrawal, and P. Bhatnagar, “A multilevel inverter structure with open circuit fault-tolerant capability,” Electrical Engineering, vol. 103, pp. 1613–1628, 2021.
[5] Y. Shen, Y. Zhang, and X. Wang, “Fault?tolerant control strategy for neutral?point?clamped three?level inverter,” Journal of Control Science and Engineering, vol. 2018, Article ID 5126404, 2018.(2002) The IEEE website. [Online]. Available: http://www.ieee.org/
[6] D. Kumar, R. K. Nema, and S. Gupta, “Development of fault?tolerant reduced device version with switched?capacitor based multilevel inverter topologies,” International Transactions on Electrical Energy Systems, vol. 31, no. 7, e12893, 2021.
[7] S. Sivapriya and R. Kumar, “Enhancing reliability in multilevel inverter: A fault?tolerant approach with reduced switch count,” International Journal of Circuit Theory and Applications, vol. 49, no. 7, pp. 1735–1750, 2021.
[8] K. S. Kumar, “A fault-tolerant single-phase five-level inverter for grid-independent PV systems,” RAE, 2015.
[9] D. Maharjan, S. Rana, and N. Paudel, “A review on multilevel inverters and their applications,” IEEE Trans. Power Electron., vol. 36, no. 5, pp. 1242–1256, 2021.
[10] J. Rodríguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 882–892, 2002.
[11] E. Babaei, M. Alilu, and S. Laali, “A new general topology for cascaded multilevel inverters with reduced number of components,” IEEE Trans. Ind. Electron., vol. 61, no. 8, pp. 3932–3941, 2019.
[12] P. Choudhary and B. Singh, “Model-based fault diagnosis and mitigation in multilevel inverters,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 8, no. 3, pp. 1124–1135, 2020.
[13] A. Kumar and S. Jain, “Fault-tolerant control of neutral-point-clamped inverters,” IEEE Trans. Power Electron., vol. 32, no. 9, pp. 7234–7243, 2017.
[14] K. Al-Haddad, H. Kanaan, and M. Ghribi, “Voltage balancing techniques for diode-clamped multilevel inverters under fault conditions,” IEEE Trans. Power Electron., vol. 36, no. 10, pp. 15547–15558, 2021.
[15] X. Li, P. Wang, and Y. Zhao, “Artificial intelligence-based fault-tolerant control strategies for multilevel inverters,” IEEE Trans. Ind. Electron., vol. 65, no. 11, pp. 8884–8893, 201