Design and Analysis of Full Adder Using Pass Transistor Logic

Authors: M Anjaneya Naik, K. Lokesh Krishna

DOI Link: https://doi.org/10.22214/ijraset.2026.80490

Abstract

There is a demand for high-performance and power-efficient arithmetic circuits in modern electronics has driven extensive research into full adder (FA) designs. This report presents the design, implementation, and comprehensive analysis of a low-power, high-speed hybrid full adder based on a 90nm CMOS process technology. The proposed system integrates separate optimized modules for SUM and CARRY generation to achieve superior performance by leveraging the strengths of different logic styles. Specially, this work details a 14-transistor(14-T) hybrid FA cell that combines the advantages of Pass Transistor Logic (PTL) and Gate Diffusion Input (GDI) techniques. The primary objective is to minimize power consumption, reduce propagation delay, and decrease the overall Power-Delay Product (PDP), which are critical metrics for applications in contemporary VLSI systems.

Introduction

The text describes a low-power, high-speed hybrid full adder design developed for modern electronics using 90nm CMOS technology. It focuses on improving performance by optimizing SUM and CARRY modules with a combination of Pass Transistor Logic (PTL) and Gate Diffusion Input (GDI) techniques in a 14-transistor design. The main goal is to reduce power consumption, propagation delay, and Power-Delay Product (PDP) for efficient VLSI applications.

Conclusion

In this work, design and analysis of a pass transistor logic (PTL) based full adder using cadence virtuoso tool. Proposed design targets reducing power and area while satisfying performance, thus applicable for modern low-power VLSI design. This report gives complete analysis of a next generation full adder using pass transistor logic (PTL). Primary objective is to develop a cost-effective, highperformance, low-power full adder. The simulation performed on 90 nm CMOS processes and proposed PTL full adder provides improvement in average power and power-delay product (PDP) compared to conventional CMOS. Also the reduced number of transistors results in lower switching capacitance. To overcome limitations of a conventional designs pass transistor logic (PTL) is introduced. This facilitates a significant reduction in transistor count, which directly leads to smaller silicon area and lower over all switched capacitance, resulting in reduced dynamic power dissipation.

References

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Copyright

Copyright © 2026 M Anjaneya Naik, K. Lokesh Krishna. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Paper Id : IJRASET80490

Publish Date : 2026-04-18

ISSN : 2321-9653

Publisher Name : IJRASET

DOI Link : Click Here