Design and Implementation of 32-bit Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol using Cadence

Abstract

TheAdvancedMicrocontroller Bus Architecture (AMBA), developed by ARM, is a widely adopted open standard that facilitates high-performance, low-power communication between functional blocks in System-on-Chip (SoC) designs. It enables modularity, scalability, and reusability in SoC development through a family of protocols including AHB (Advanced High-performance Bus), AXI (Advanced extensible Interface), and APB (Advanced Peripheral Bus). Among these, APB is specifically designed for connecting simple, low-bandwidth peripherals such as UARTs, timers, and GPIOs due to its low complexity and reduced power consumption.This work presents the Design and Implementation of 32-bit AMBA APB Protocol using Cadence, showcasing a complete digital VLSI design flow. The project encompasses RTL coding in Verilog HDL, functional verification using testbenches, and synthesis using Cadence Genus to evaluate area, power, and delay reports. Following synthesis, the design undergoes placement and routing in Innovus, resulting in a GDSII layout generation. Post-synthesis and post-layout analyses are carried out to ensure that the design meets performance and physical constraints. The final GDS file confirms successful implementation from RTL to layout, making the protocol ready for silicon realization. This project demonstrates the integration of bus protocol design within a professional EDA environment, reflecting industry practices in hardware development and physical design.

Introduction

System-on-Chip (SoC) designs increasingly rely on efficient, low-power internal communication protocols. ARM’s AMBA standard, particularly the Advanced Peripheral Bus (APB), addresses this by providing a simplified, low-bandwidth interface for peripherals like UARTs, timers, and GPIOs. APB’s straightforward master-slave protocol uses key signals to ensure synchronized, deterministic data transfer with minimal power and area overhead.

This work focuses on the design and implementation of a 32-bit AMBA APB protocol using Verilog HDL, verified through simulation and synthesized with Cadence Genus, followed by physical layout in Cadence Innovus. The project addresses key challenges such as protocol correctness, timing closure, and physical constraints to produce a silicon-ready design.

The APB master controls communication by selecting slaves and managing read/write operations, while slaves respond with data or error signals. The design incorporates a finite state machine to manage APB states and uses a 32x32-bit memory block in the slave for data storage. Functional verification through a Verilog testbench confirms protocol compliance and correct operation.

Synthesis results demonstrate the design’s efficiency with a total area of about 20,086 µm², positive timing slack, and power consumption under 200 µW. The physical design flow includes floorplanning, placement, clock tree synthesis, routing, and optimization, culminating in a GDSII layout ready for fabrication.

This comprehensive, industry-standard approach provides a valuable educational and practical reference for low-power peripheral communication IP design within modern SoCs.

Conclusion

In this project, the design and implementation of a 32-bit AMBA APB (Advanced Peripheral Bus) protocol were successfully carried out using Verilog HDL for RTL modeling and Cadence tools for synthesis and physical design. Verification was performed through an efficient Verilog Testbench, which tested various operational scenarios including Read, Write, and Error cycles, ensuring the functional correctness of the protocol. The testbench incorporated reusable tasks and self-checking mechanisms for validating different data paths and memory operations. The integration of design and testbench through interface logic allowed seamless simulation and verification. Random data and index-based test cases were used to verify the robustness of the design. Simulation results confirmed that the data retrieved during the read cycle accurately matched the data written, confirming the correctness of the protocol behaviour. The complete flow from RTL to GDSII was executed using Cadence Innovus, covering steps such as synthesis, floor planning, power planning, placement, clock tree synthesis (CTS), routing, and final GDSII generation. The final layout was verified for design rule correctness and functional equivalence. This work demonstrates a full-cycle implementation of the AMBA APB protocol, from design and verification to physical realization. For future scope, low-power design techniques can be incorporated to further enhance the efficiency and performance of the APB protocol in SoC environments.

References

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Copyright

Copyright © 2025 P. Uma Maheshwari , J. Siddhu Nayak, Sreeja Mandava, M. Shoukath Ali. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.