Design and Implementation of Low Power 4:2 Compressor using GDI Technique

Abstract

The objective is to develop a 4:2 compressor with GDI technique (Gate Diffusion Input). This is specifically aimed at reducing power consumption and digital circuit delays. The proposed GDI-based 4:2 compressor is compared to two existing designs: traditional CMOS design and 8T XOR-XNOR design. The results show that the GDI design saves 75.34% of the power consumptioncompared to traditional CMOS designs and 48.81% compared to the 8T XOR- XNOR designs. One of the main applications of this compressor is the design of multipliers, which is essentially important for efficient arithmetic operations in digital systems.The implementation of a GDI based 4:2 compressor in multiplier design improves the overall performance of the multiplier, achieving both faster calculations and lower energy consumption. When integrating the compressor with the 4x4 multiplier. The proposed design saves 51.24% of power supply compared to traditional CMOS design and 31.42% of power supply compared to 8T XOR-XNOR designs.

Introduction

The design of low-power digital circuits is critical for modern VLSI systems, especially in portable and high-performance applications where energy efficiency matters. A fundamental component in arithmetic and signal processing units is the 4:2 compressor, used to reduce four input bits into two output bits plus a carry, thereby optimizing complex computations like multipliers and adders.

Traditional CMOS-based 4:2 compressors consume high power and use many transistors, leading to larger area and slower switching speeds. This project proposes using Gate Diffusion Input (GDI) technology to design a 4:2 compressor that reduces transistor count, power consumption, and delay, enhancing speed and efficiency for VLSI applications.

The design methodology involved implementing the GDI-based 4:2 compressor in 90nm CMOS technology, integrating it into a 4x4 multiplier, and simulating the circuits using Cadence Virtuoso. Results show the GDI compressor outperforms conventional CMOS designs and an 8-transistor XOR-XNOR design, achieving lower power consumption (8.92 µW vs. 36.19 µW) and reduced delay (357.4 ps vs. 604.4 ps).

Similarly, the 4x4 multiplier using the GDI-based compressor consumed significantly less power (1.1 mW) compared to CMOS (3.5 mW) and 8T XOR-XNOR (1.8 mW) designs.

Overall, the GDI technique enables faster, more power-efficient compressors suitable for digital signal processing and embedded systems, making it a promising approach for energy-efficient arithmetic circuits in modern VLSI design.

Conclusion

The 4:2 compressor designed using the GDI technique achieves low power consumption and minimal delay by reducing the number of transistors and logic complexity. This results in improved efficiency, making it ideal for high-performance and low-power VLSI applications, such as multipliers and DSP systems.This GDI based 4:2 compressor is compared with two existing designs. By comparing it with conventional CMOS design, it saves 75.34% of power and with 8T XOR-XNOR design, it saves 48.81% of power. This GDI design results in faster switching speed and reduced power consumption, making it ideal for high-performance and low-power VLSI applications, such as multipliers and DSP systems. To appreciate the performance of the proposed GDI based compressor, a 4x4 array multiplier is implemented using the proposed compressor. This provides a saving of 51.24% of power consumption compared to conventional CMOS based multiplier and 31.42% of power consumption compared to the 8T XOR-XNOR module based multiplier.

References

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Copyright

Copyright © 2025 Dr. H. Mangalam, Narmatha A, Raja Lekshmi S, Karpaga Kumar U K. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.