Distributed arithmetic technique is employed in this paper to develop the FIR filter. To eliminate undesired signal and noise, FIR filters are frequently employed as digital filters in digital signal processing. This method also calls for shift registers and an accumulator and stores the FIR filter coefficients in a look-up table (LUT).By using this method, shift and accumulate can take the place of the multipliers in the FIR filter. The size of the LUT can be reduced for larger filter coefficients by dividing it into any number of LUTs, which are made up of taps that are FIR filter coefficients. FIR filter is created in MATLAB using the DA technique, and manual computation yields the same result.
Digital signal processing use FIR filters for a variety of purposes, including frequency selection, smoothing, and noise reduction. The complexity and power consumption of the FIR filter are increased by the necessity of a large number of multipliers to implement the necessary filter coefficients. By lowering the quantity of multipliers necessary for filter design, this problem can be resolved. The computation complexity of the multiplication operations employed in the filter design is reduced by the use of distributed arithmetic in the construction of FIR filters. This method substitutes another operation for multiplication. Page Layout
A. FIR filter with Multiplier
A finite number of input samples are used by the FIR filter to generate a finite number of output responses. It is chosen because it produces a linear phase response as a result of the symmetry of the filter coefficients. In a linear phase response, each component is delayed by the same amount of time and is also helpful in maintaining the phase of the signal, which is helpful in applications for image processing and audio. Each input sample is multiplied by a corresponding filter coefficient in order for the filter to work on the input signal. The results are then added together to create the filtered output sample.
The filter coefficients can be used to calculate the frequency response of a filter, allowing for the design of a variety of filters, including high-pass, low-pass, band-pass, and band-stop filters.Windowing approach can be used to create the necessary filter taps or coefficients by multiplying the desired frequency response by the window function.Least Square and Parks McClellan are two additional implementation strategies that can be employed for filter design.Based on filter performance metrics including ripple, transition bandwidth, and attenuation, the FIR filter is chosen.FIR filters are preferred over IIR filters due to its advantages such as linear phase response, stability, and the possibility to construct same frequency responses.
B. FIR filter design using Distributed arithmetic
Digital signal processing uses the Distributed arithmetic technique to carry out computations quickly and effectively.This method replaces the standard addition and multiplication operations with algorithms that are implemented on hardware to save FPGA resources.This method lessens the number of arithmetic operations, which in turn lessens the complexity of the hardware. It is used to substitute a Look Up Table and a shifter-accumulator for all multiplications and additions. Multiplying c[n]x[n] results in a multiplication by a constant because DA depends on knowing the filter coefficients.
The above image depicts the block design for the DA for FIR filter. When implementing DA, the number of inputs that must be stored must match the length of the coefficients in each buffer stage. Then, the LSB bits of each coefficient are used as the LUT's address.To accept an N-bit address, where N is the number of coefficients, a 2n word LUT is preprogrammed to do so.Each mapping is given the proper weight by the combined effect of two elements.A shift-adder is effectively used to implement the accumulation.For hardware implementation, shift the accumulator content itself in each direction by one bit to the right rather than shifting each intermediate value by power factor, which necessitates an expensive barrel shifter.
Below gives the explanation of distributed arithmetic technique:
1) Generation of coefficients for sampling frequency= 4KHz, Fpass = 60Hz, Fstop = 400Hz, Apass = 0.1dB, Astop = 60dB from MATLAB FDA tool and stored in a text file
Finite impulse response filters are frequently used in digital signal processing applications. The multiplier-less FIR filter is built using distributed arithmetic, which incorporates a look-up table and partitioning. Memory access takes longer than multiplication. LUT split reduces the need for memory. His approach reduces the amount of time, space, and power used. This architecture delivers an effective area-time power implementation with a great deal reduced latency and area-delay complexity when compared to other FIR Filter topologies.
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 Meher P K, Chandrasekaran S, et al., \\\"FPGA realisation of FIR filters by efficient and flexible systematisation using distributed arithmetic,\\\" IEEE Transactions on Signal Processing, vol. 56(7).