Energy Efficient Compact Approximate Multplier for Error-Resilient Applications

Abstract

This study focuses on enhancing system performance through approximate computing by proposing efficient 8-transistor and 20-transistor 4:2 compressors for approximate multipliers. These designs leverage CMOS technology with constant and conditional approximation techniques to minimize errors while eliminating the need for an error recovery module. The 20-transistor compressor achieves higher accuracy at a slight area cost, while the proposed multiplier demonstrates a 50% reduction in area and a 93% improvement in power-delay-product compared to exact multipliers.

Introduction

This study presents a novel, energy-efficient approximate 8-bit multiplier that leverages two new majority logic (ML)-based compressor designs:

• ACMLC (Approximate Condition-Based Majority Logic Compressor)

• CAC (Compensator Approximate Compressor)

These compressors aim to reduce hardware complexity, power consumption, and area while maintaining acceptable accuracy—especially for error-tolerant applications like image processing.

Key Contributions:

1. Compressor Design:

   • 8-transistor ACMLC minimizes hardware requirements.

   • 20-transistor CAC improves accuracy.

   • Together, they eliminate 15 AND gates and reduce the need for exact compressors.

   • Achieve 49% area reduction and 93% lower energy use compared to exact multipliers.

2. Approximate Multiplier Architecture:

   • Combines truncation, approximation, and exact computation.

   • Truncates 4 least significant bits using constant assignment (0110), eliminating 10 AND gates.

   • Uses a mix of ACMLC, CAC, and minimal exact adders to form a highly efficient multiplier.

3. Performance:

   • 786 total transistors (vs. 900 in ML-based and 1530 in exact multipliers).

   • Power consumption: 6.386 W (98% dynamic).

   • Logic delay: ~3.9 ns; Total delay: ~9.2 ns.

   • Uses only 31 LUTs and 10 slices, showing excellent area efficiency.

Conclusion

In this paper, we proposed an 8-transistor ACMLC compressor, a 20-transistor CAC, and an approximate 8-bit multiplier for accurate and efficient image multiplication. The compressor has small footprint and low power consumption at the expense of a relatively high error rate. To compensate for the negative errors, we propose CAC, exhibiting seven errors, with only one being negative. We propose an ACMLC/CAC-based approximate multiplier to exploit the proposed compressors’ unique characteristics. Relative to an exact multiplier, the proposed multiplier exhibits 50% area reduction and 93% power savings. The proposed multiplier exhibits superior performance across most evaluated metrics compared to state-ofthe-art approximate multipliers. The Pareto results reveal that despite their lower accuracy, ML-based proposed circuits are promising for low-power and energy dissipation applications.

References

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Copyright

Copyright © 2025 Muktesha Mani Pradeep Sarma Jonnalagadda, Saikrishna Dabbakuti, Raju Gumma, Tirupati Rao Karumanchi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.