Low Power Two Stage CMOS Operational Amplifier

Abstract

Operational amplifier (Op-Amp) circuits play a critical role in computation, instrumentation, and a variety of industrial applications. With the growing demand for precision Op-Amps in automotive and industrial environments, there is an increasing need for designs that offer enhanced accuracy and robust performance across wide temperature ranges. The shift towards integrating both analog and digital circuits on a single chip has made Complementary Metal-Oxide Semiconductor (CMOS) technology the preferred choice over traditional bipolar technologies for analog circuit design in mixed-signal systems. Among various Op-Amp topologies, the two-stage architecture remains one of the most widely adopted due to its favorable gain and output swing characteristics. This paper presents the design and simulation of a CMOS-based two-stage fully differential operational amplifier, optimized for low-power and low-voltage operation. The amplifier is biased with a current of 20 µA and is implemented using both 180 nm and 90 nm CMOS process technologies. Special emphasis is placed on operation in the sub-threshold region, where the unique behavior of MOS transistors facilitates ultra-low-voltage and low-current operation. The proposed Op-Amp is intended for on-chip applications with capacitive load requirements in the picofarad range. Simulation results are obtained using the Cadence Virtuoso design environment and demonstrate the performance of the amplifier across key parameters in both technology nodes. Tools: Cadence Virtuoso

Introduction

I. Background and Motivation:

• The demand for compact, energy-efficient electronics (e.g., in telecommunications, medical devices, and consumer electronics) has driven the trend toward low-voltage, low-power silicon chip design.

• Operational Amplifiers (Op-Amps) are vital in analog signal processing for functions such as amplification, filtering, and buffering.

• Op-Amps are widely used due to their versatility, cost-effectiveness, and support for precise signal manipulation via negative feedback.

• A voltage follower configuration demonstrates their high input impedance and ability to isolate circuit stages without signal degradation.

II. Existing Systems:

• Prior designs include:

  • Priyanka et al.: A two-stage CMOS Op-Amp (180 nm tech) operating at 1.8 V, achieving 63 dB gain, 140 kHz bandwidth, 32 V/µs slew rate, and 300 µW power consumption.

  • Swami and Rai: High-gain Op-Amp emphasizing wide output swing and high common-mode rejection through iterative W/L ratio tuning and simulation-based optimization.

III. Proposed System:

• A two-stage CMOS Op-Amp is designed using 90 nm process technology, targeting:

  • High speed

  • Low power consumption

  • Area efficiency

• The design employs advanced circuit techniques to reduce propagation delay and supports scalability for integration into various digital signal processing systems.

IV. Simulation Results:

• Transient Analysis (Fig. 3): Tested with a 1 µs input pulse width and 3 µs period to verify voltage and current behavior.

• Power Analysis (Fig. 4): Confirms low-power characteristics suitable for battery-operated systems.

• Noise Analysis (Fig. 5): Evaluates the amplifier’s performance in minimizing signal distortion and interference.

Conclusion

\"This work presents the design and characterization of a high-performance two-stage CMOS operational amplifier in a 90nm CMOS process, successfully meeting all specified design parameters. Notably, the design achieves enhanced gain, slew rate, and a wide unity-gain phase margin, demonstrating its suitability for demanding analog applications. While minor discrepancies between simulation and theoretical calculations were observed, attributable to simplifications inherent in analytical modeling, the theoretical framework provided a robust foundation for the design process. Comprehensive simulations, conducted using Cadence Virtuoso, validated the design\'s functionality, showcasing a near rail-to-rail output voltage swing achieved by operating current-sourcing transistors in the deep triode region.

References

[1] S. Pourashraf, J. Ramirez-Angulo, A. J. Lopez-Martin and R. González-Carvajal, \"A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads,\" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2061-2072, Oct. 2018, doi: 10.1109/TVLSI.2018.2830365. [2] Paul, J. Ramírez-Angulo, A. J. López-Martín, R. G. Carvajal and J. M. Rocha-Pérez, \"Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance,\" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2246-2259, Oct. 2019, doi: 10.1109/TVLSI.2019.2918235. [3] L. Liu, M. Chen, W. Huang, X. Liao and J. Xu, \"A High Current-Efficiency Rail-to-Rail Class-AB Op-Amp With Dual-Loop Control,\" in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4218-4222, Nov. 2022, doi: 10.1109/TCSII.2022.3187979. [4] K. O. Petrosyants, L. M. Sambursky, M. V. Kozhukhov, M. R. Ismail-Zade, I. A. Kharitonov and B. Li, \"SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From ?200 °C to +300 °C),\" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, pp. 708-722, April 2021, doi: 10.1109/TCAD.2020.3006044. [5] A. Parthipan, K. L. Krishna, V. N. Kumar, C. Hareesh, B. Raviteja and C. V. Varshath, \"A High Performance CMOS Operational Amplifier,\" 2019 3rd International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, 2019, pp. 702-706, doi: 10.1109/ICCMC.2019.8819641. [6] N. Prokopenko, V. Chumakov and A. Bugakova, \"CMOS Operational Amplifier With Low Level of the Systematic Component of the Zero Offset Voltage,\" 2022 International Conference on Actual Problems of Electron Devices Engineering (APEDE), Saratov, Russian Federation, 2022, pp. 163-166, doi: 10.1109/APEDE53724.2022.9912820 [7] A. Yadav, N. Rai, A. Verma and S. Wairya, \"Design of Flash ADC using low offset comparator for analog signal processing application,\" 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2021, pp. 76-81, doi: 10.1109/SPIN52536.2021.9566050. [8] Allen.P.E., and Holberg.D.R., “CMOS Analog circuit design” Third Edition, 2019, Oxford University Press. [9] R.Jacob Baker, “CMOS: Circuit Design, Layout, and Simulation”, Third Edition, 2012, Wiley-IEEE Press. [10] Carusone.T.C. et al.,“Analog Integrated Circuit Design”, John Wiley & Sons, Inc. 2016 Second Edition, NJ. [11] K. S. Kumar, K. L. Krishna, K. S. Raghavendra and K. Harish, \"A High Speed Flash Analog to Digital Converter,\" 2018 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), 2018 2nd International Conference on, Palladam, India, 2018, pp. 283-288, doi: 10.1109/I-SMAC.2018.8653782. [12] S. P. Surabhi and Deepa, \"Design and Analysis of Low Power High Gain Amplifiers for DAC Application,\" 2022 IEEE International Conference on Data Science and Information System (ICDSIS), Hassan, India, 2022, pp. 1-6, doi: 10.1109/ICDSIS55133.2022.9915853. [13] N. Prokopenko, A. Titov, V. Chumakov and A. Bugakova, \"The Circuit Technique for Reducing the Zero Level of the JFET Op-Amp on the Push-Pull Folded-Cascode,\" 2022 IEEE International Multi-Conference on Engineering, Computer and Information Sciences (SIBIRCON), Yekaterinburg, Russian Federation, 2022, pp. 1310-1313.

Copyright

Copyright © 2025 D. Guru Poojitha, C. Thoshitha , S. Venkatesh , K. Puneeth, B. Vishnu Prasad, A. Arius Rakesh . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.