Power Optimization for Enhanced Data Transmission in VLSI Router Buffers

Abstract

One essential component of contemporary communication systems is the planning and execution of effective routing topologies. In this research, a redesigned VLSI-based router architecture optimized for low power consumption and fast data transmission speed is proposed. The suggested architecture and state-of-the-art VLSI design approaches to provide efficient data routing to any of the outputs. Through simulations, the design\'s performance is assessed. The simulation was run using the VHDL programming language in Xilinx software. The design includes the Arbiter, Cross Bar, and FIFO blocks. A major step toward the creation of high-performance communication systems has been made with this study. In the proposed method by using clock gating the overall power of the design and delay and area will be reduced compared to the existing architecture.

Introduction

The Network-on-Chip (NoC) architecture has become essential for handling the growing number of cores in System-on-Chip (SoC) designs, overcoming limitations of traditional SoC communication such as low core utilization, poor scalability, and complexity. NoC design depends on key components like FIFO buffers, routers, arbiters, and crossbars, as well as routing strategies and network topologies to efficiently manage data flow between processing units.

• FIFO Buffers: Enable smooth data transfer between CPU and peripherals, following first-in-first-out order, with adjustable capacity affecting performance and connection reliability.

• Routers: Forward packets between networks (LANs and WANs), forming larger internetworks and enabling communication between multiple devices.

• Round Robin Arbiter: Allocates shared resources fairly among competing units in a cyclic manner, preventing conflicts on shared buses.

• Crossbar: Allows multiple simultaneous processor-to-processor or processor-to-memory communications without contention, critical in high-performance SoC designs.

The text also highlights flow routing, which adapts packet routing based on real-time traffic conditions, improving efficiency for streaming data. SoC integration relies on combining diverse expertise and IPs from specialized domains while shifting design focus from computation-centric to communication-centric approaches.

Existing methods implement FIFO, crossbar, and arbiter blocks using structural modeling; however, routing is limited to fixed directions (center-to-center, north-to-north, south-to-south).

Proposed methods improve data routing efficiency by integrating Round Robin arbitration with modified crossbars (4×1 and 8×1 multiplexers), allowing flexible, high-throughput data paths. Simulation and X-Power analysis assess power consumption and functional performance, emphasizing scalable, optimized NoC design for modern SoCs.

Conclusion

The work focuses on optimizing the performance of VLSI based router architecture. From comparison table we can infer the comparison of the existing router model and the proposed router model. The proposed model increases the efficiency of data transmission by compared to the existing model. This is achieved by adding multiplexers in the crossbar at the output port and negative edge D latch. In proposed method of VLSI Router for the Faster Date Transmission using Buffer the power of the design was reduced by 0.122w and area, delay was also getting reduced.

References

[1] T. A. C. M. Claasen, \"An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology,\" in Proceedings of the IEEE, vol. 94, no. 6, pp. 1121-1137, June 2006, doi: 10.1109/JPROC.2006.873616. [2] G. Martin and H. Chang, \"System-on-Chip design,\" ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), Shanghai, China, 2001, pp. 12-17, doi: 10.1109/ICASIC.2001.982487. [3] Giechaskiel, Ilias, and Jakub Szefer. \"Information leakage from FPGA routing and logic elements.\" Proceedings of the 39th International Conference on Computer-Aided Design. 2020. [4] M. Katta and Ramesh, T. K., “Latency Improvement by using FILL VC Allocation for Network on Chip”, in International Conference on Data Engineering and Communication Technology (ICDECT) 2020, Kakatiya Institute of Technology and Science, Warangal, 2020. [5] N. Varghese and Swaminadhan R., “Power Efficient Router Architecture for Scalable NoC”, Innovations in Electronics and Communication Engineering. Springer Singapore, Singapore, 2020. [6] Wang, Xin, Tapani Ahonen, and Jari Nurmi. \"A synthesizable RTL design of asynchronous FIFO.\" 2004 International Symposium on System-onChip, 2004. Proceedings IEEE, 2004. [7] Wanjari, Minakshi M., Pankaj Agrawal, and R. V. Kshirsagar. \"Design of NOC router architecture using VHDL.\" International Journal of Computer Applications 115.4 (2015). [8] Balharith, Taghreed, and Fahd Alhaidari. \"Round robin scheduling algorithm in CPU and cloud computing: a review.\" 2019 2nd International Conference on Computer Applications & Information Security (ICCAIS). IEEE, 2019 [9] Verma, Gaurav, et al. \"Design and implementation of router for NOC on FPGA.\" International Journal of Future Generation communication and networking 9.12 (2016): 263-272. [10] Venkataraman, N. L., Rajagopal Kumar, and P. Mohamed Shakeel. \"Ant lion optimized bufferless routing in the design of low power application specific network on chip.\" Circuits, Systems, and Signal Processing 39.2 (2020): 961-976. [11] S. Madhavan and H. P. V, \"Design and Verification of 1X5 ROUTER,\" 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon), Mysuru, India, 2022, pp. 1-6, doi: 10.1109/MysuruCon55714.2022.9972633. [12] J. A. Williams, N. W. Bergmann and X. Xie, \"FIFO communication models in operating systems for reconfigurable computing,\" 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\'05), Napa, CA, USA, 2005, pp. 277-278, doi: 10.1109/FCCM.2005.35. [13] J. T. Han, Y. Guan and Z. Dai, \"Implementation of SoC-PC Communication Interface Based on USB2.0,\" 2009 International Conference on New Trends in Information and Service Science, Beijing, China, 2009, pp. 831-834, doi: 10.1109/NISS.2009.53. [14] J. T. Han, Y. Guan and Z. Dai, \"Implementation of SoC-PC Communication Interface Based on USB2.0,\" 2009 International Conference on New Trends in Information and Service Science, Beijing, China, 2009, pp. 831-834, doi: 10.1109/NISS.2009.53. [15] M. Oveis-Gharan and G. N. Khan, \"Index-Based Round-Robin Arbiter for NoC Routers,\" 2015 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, 2015, pp. 62-67, doi: 10.1109/ISVLSI.2015.27. [16] A. Mangukia, M. Ibrahim, S. Golamudi, N. Kumar and M. Anand Kumar, \"Improved Variable Round Robin Scheduling Algorithm,\" 2021 12th International Conference on Computing Communication and Networking Technologies (ICCCNT), Kharagpur, India, 2021, pp. 1-7, doi: 10.1109/ICCCNT51525.2021.9579716. [17] W. Ullah and M. A. Shah, \"A novel resilent round robin algorithm based CPU scheduling for efficient CPU utlilization,\" Competitive Advantage in the Digital Economy (CADE 2022), Hybrid Conference, Venice, Italy, 2022, pp. 41-48, doi: 10.1049/icp.2022.2038. [18] Hassan, Syed Minhaj, and Sudhakar Yalamanchili. \"Centralized buffer router: A low latency, low power router for high radix nocs.\" 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS). IEEE, 2013. [19] B. Zhao, Y. Zhang and J. Yang, \"A speculative arbiter design to enable high-frequency many-VC router in NoCs,\" 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, 2013, pp. 1-8, doi: 10.1109/NoCS.2013.6558415. [20] G. Xiaopeng, Z. Zhe and L. Xiang, \"Round Robin Arbiters for Virtual Channel Router,\" The Proceedings of the Multiconference on \"Computational Engineering in Systems Applications\", Beijing, China, 2006, pp. 1610-1614, doi: 10.1109/CESA.2006.4281893.

Copyright

Copyright © 2025 Shaik Shahina Parveen, Dr. S. Arunamastani. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.