A Second Order True VCO ADC Applying a Digital Pseudo DCO Apt for Sensor Arrays

Abstract

This paper presents a power-efficient, second-order VCO-based analog-to-digital converter (ADC) implemented in 45?nm CMOS technology. The proposed architecture employs a power-gated, current-starved 7-stage ring VCO using MCML and a fully digital pseudo-DCO. By integrating sleep transistors and hardware-level gating, the design achieves a 66% reduction in total power consumption—from 1088.1?µW to 369.9?µW—while maintaining 4-bit resolution and a 1?MHz sampling rate. The scalable pseudo-DCO enables binary-weighted frequency generation, dynamic resolution control via Over-Running Ratio (ORR) tuning, and efficient multi-channel sharing. This digital-centric approach reduces reliance on complex analog blocks, enhances robustness in advanced nodes, and supports compact, low-power integration. This architecture is well-suited for battery-constrained applications such as wearable health monitors, implantable sensors and edge IoT devices.

Introduction

The text presents a power-efficient, second-order VCO-based ADC architecture designed for low-power, high-resolution applications such as biomedical devices, wearable electronics, and IoT sensors. Traditional analog-to-digital converters (ADCs) are increasingly being replaced by digitally dominant architectures due to the demand for low power, high integration, and robustness against process-voltage-temperature (PVT) variations.

Key Features and Innovations:

1. VCO-Based ADC Architecture:

   • Uses a Voltage-Controlled Oscillator (VCO) to convert analog voltage into a frequency-modulated signal.

   • Replaces traditional analog components (e.g., comparators and integrators) with digital pulse frequency modulation (PFM) and noise shaping.

   • Offers digital compatibility, scalability, and low power consumption.

2. Power Optimization Techniques:

   • Power-gated, current-starved ring VCO reduces both dynamic and leakage power during idle periods using sleep transistors and dual-threshold MOSFETs.

   • Incorporates MOS Current Mode Logic (MCML) for enhanced noise immunity and frequency stability.

   • Implements the Pull-Up Sleepy technique using special PMOS devices to further reduce leakage current in inactive states.

3. Digital Pseudo-DCO:

   • A fully digital oscillator generates binary-weighted frequencies using sequence generators.

   • Supports Over-Running Ratio (ORR) scaling, enabling dynamic adjustment of resolution, power, and multi-channel operation.

   • Highly compact and CMOS-compatible compared to LC oscillator designs.

4. Frequency-to-Digital Converter (FDC):

   • Converts the VCO’s output frequency into a digital value using a resettable counter.

   • Count reflects frequency over a fixed time window, directly translating input voltage to a digital code.

   • Ensures monotonic behavior, low latency, and high speed, making it reliable for energy-constrained systems.

Applications and Impact:

The proposed ADC achieves:

• High-resolution conversion with minimal analog circuitry.

• Low power consumption, crucial for long-duration and wearable applications.

• Compactness and scalability, making it suitable for multi-channel sensor arrays and future edge AI devices.

Conclusion

This paper presents a power-efficient, second-order VCO-based ADC architecture that integrates a power-gated, current-starved 7-stage ring VCO using MCML and a fully digital pseudo-DCO, implemented in 45?nm CMOS technology. By incorporating sleep transistors and hardware-level gating, the design achieves a 66% reduction in total power consumption—dropping from 1088.1?µW to 369.9?µW—while maintaining 4-bit resolution and a 1?MHz sampling rate. The scalable pseudo-DCO supports binary-weighted frequency generation, dynamic resolution control via Over-Running Ratio (ORR) tuning, and efficient multi-channel sharing, enhancing flexibility for SoC integration. By seamlessly combining digital control, frequency-domain processing and power-optimized circuit techniques, the proposed ADC delivers a compact, high-performance solution ideally suited for next-generation ultra-low-power applications in biomedical monitoring, wearable systems and IoT edge platforms.

References

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Copyright

Copyright © 2025 Jai Sowmiya R, Santhi M. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.